1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the device, and particularly to a floating gate EEPROM in which an inter-poly dielectric film is thinned and a method for manufacturing the EEPROM.
2. Description of the Related Art
Semiconductor devices include a rewritable nonvolatile memory referred to as a floating gate electrically erasable programmable read-only memory (EEPROM). One example of such a floating gate EEPROM is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 11-204788, for example. In order to make this floating gate EEPROM smaller, it is necessary to reduce thickness of a tunnel gate dielectric film or an inter-poly dielectric (IPD) film. However, if the IPD film is reduced in thickness, there increases a danger that a leakage current is easily generated or the leakage current increases. If the leakage current is generated or increases, data holding characteristics of a nonvolatile memory easily deteriorates. Therefore, it is difficult to thinly form the IPD film in order to maintain data holding characteristics of the nonvolatile memory.
There exists a technique of three-dimensionally forming memory cells (capacitors) in order to obviate a tradeoff problem between maintenance of the data holding characteristics of such a nonvolatile memory and size reduction of the EEPROM due to reduction of the IPD film in thickness. According to this technique, a square area of the IPD can be increased without reduction of its thickness. Thus, the data holding characteristics of the nonvolatile memory can be maintained while generation and increase of a leakage current are restrained. In other words, the EEPROM can be made smaller while the capacitance of memory cells is maintained.
However, even if a three-dimensional capacitor structure is employed, it is impossible to avoid reduction of the IPD film in thickness in order to enable further size reduction of the EEPROM. One of the reasons is that the space between control gate electrodes is embedded with the IPD. If the IPD film is reduced in thickness in a three-dimensional capacitor structure, electric field concentration easily occurs at corner portions (top corner portions) of a floating gate electrode that comes into contact with the IPD film rather than planer portions (flat portions) such as top surface and side surface of the floating gate electrode that comes into contact with the IPD film. As a result, a leakage current easily flows at the corner portions of the floating gate electrode. As a result of these processes, electric charges accumulated on the floating gate electrode are released, and thus, the data holding characteristics of the nonvolatile memory deteriorates. In other words, when a three-dimensional capacitor structure is employed, reduction of the IPD film in thickness first reaches a limit at the corner portions of the floating gate electrode.